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Altera_Forum's avatar
Altera_Forum
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17 years ago

Error placing clock pin with Clock Control Block

Hello all,

It appears I could use some assistance.

Some background ... The device is an EP2SGX130F1508. The problem in question concerns two clock inputs. The two clock inputs are from the dedicated transceiver reference clock pins.

Both clock inputs are brought into a Clock control block (ALTCLKCTRL megafunction) which I use to dynamically select between the two input clocks.

During the fitter stage, the compilation errors out with: 

Error: Can't place sdi_clkref_p at location PIN P7 because it uses a Clock Control Block with dynamic clock select

My supposition is that it's preventing me from doing this because the clocks are located in the transceiver quad.

Any ideas?

Jake

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    As far as I understand, there are various reconfiguration options for GX clocks, but they don't use regular clock control blocks. The dedicated ref clock inputs are wired directly to the GX PLL reference clock multiplexers. A clock reconfiguration can either utilize this multiplexers or occur after the PLLs.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    FvM,

    You are correct, multiplexing of the GX transceiver PLL input reference clocks is handled via the ALT2GXB_RECONFIG megacore.

    However, I also use the reference clock for other functions within the FPGA core. Specifically in this case, the two reference clocks are two different frequencies used to generate different broadcast video standards using the GX transceivers.

    In addition to this, I also use the reference clocks directly to generate a video sync (black burst, tri-level, etc.) signal via an external DAC. I need to switch between the two clocks in order to generate different standards.

    Anyway, I've changed the code to just do the muxing in an LCELL and placing the output on a global buffer.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I think only one signal can get onto the altclkcttrl block from the fabric, and it is selected statically(i.e. at configuration), rather than dynamically. The Handbook should have a section explicitly showing the altclkctrl muxes. What you're doing is fine, but you want to be careful not to switch between clocks in such a way that you get a clock glitch, which is very easy to do.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Rysc,

    Agreed. In this particular case, all synchronous logic clocked by the muxed clock (i.e. the sync generator) is completely disabled and held in reset while the clock switchover takes place.

    Jake