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Honored Contributor
Honored ContributorError placing clock pin with Clock Control Block
Hello all, It appears I could use some assistance. Some background ... The device is an EP2SGX130F1508. The problem in question concerns two clock inputs. The two clock inputs are from t...
Altera_ForumHonored Contributor
Honored ContributorRysc,
Agreed. In this particular case, all synchronous logic clocked by the muxed clock (i.e. the sync generator) is completely disabled and held in reset while the clock switchover takes place. Jake
