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Altera_Forum
Honored Contributor
13 years agoI found the cause of the error myself. I would like to post here as this may help others when encountering the same issue. Actually, I was trying to tap some ports of an ALTGXB instantiation and these are 'untappable signal'. As mentioned in the Quartus II Handbook, chapter 13. Design Debugging Usign the SignalTap II Logic Analyzer, there are several types of signals that can not be tapped, including JTAG port, any ports of ALTGXB, data output from SERDES (LVDS) and DQ, DQS signals.