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Altera_Forum
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14 years ago

Error: Input port "DPRIOCLK" must be driven by the same source

Hi, I facing the problem with the GXB Reference clock routing. My design insatnces are PCIe, HD-SDI Receiver and SD-SDI Receiver. i connected the GXB calibration clock output of PCIe to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

I have corrected the foolish thing what i did. the tool is clearly define the issue but i cant not able to catch due to tool gives an error relating to internal signals of mega core which i was not known.

The DPRIOCLK is the The dynamic partial reconfigurable I/O {sdi_reconfig_clk} which should be driven by the same clock source of all ip channels.

Thanks.