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Honored Contributor
Honored ContributorError in Modulesim verilog
my program is compile successfully without saving but when i save the project transcript shows error unexpected integers error module auto_segment (output [6:0]hex 0,input clk); integer c...
Altera_ForumHonored Contributor
Honored ContributorHi Adnan Riar,
Error in line 4. remove semicolon from always statement. Please find the correct code.module auto_segment(output hex,input clk);
integer count;
always@(posedge clk)
begin
if(count<9)begin
count<=count + 1;
end
else begin
count<=0; end
end
endmodule
