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Altera_Forum
Honored Contributor
Honored ContributorError in Modulesim verilog
my program is compile successfully without saving but when i save the project transcript shows error unexpected integers error module auto_segment (output [6:0]hex 0,input clk); integer c...
Altera_ForumHonored Contributor
Honored ContributorYou also don't have either an initial value (integer count = 0;), or a reset signal, meaning modelsim will never output anything other than 'xxxxx' for count because there is never any time that it gets set to a known value, not depending on its current value.
