Error in Modulesim verilog

always@(posedge clk);

Notice the semi-colon after the always? It shouldn't be there - you basically ended the always block after that line.

Always indent your code properly, and always use begin and end statements after each "always", "if", "else", "for", and "initial" block. Even if that statement is just one line. It makes it far easier to see what is going on.

I also always put the begin on the same line as the "always"/"if"/"else"/etc. statement because it's easier to avoid making mistakes like semi-colons where they shouldn't be.