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Altera_Forum's avatar
Altera_Forum
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8 years ago

Error in Modulesim verilog

my program is compile successfully without saving but when i save the project transcript shows error unexpected integers error module auto_segment (output [6:0]hex 0,input clk); integer c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

HI,

Try changing your code from integer count; to reg [3:0] count;

Thanks.

Regards,

spdl2001

(This message was posted on behalf of Intel Corporation)