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Honored Contributor
Honored ContributorError Found, when I use LogicLock to constraint my design!
HI! Everybody! The FPGA is EP1C3T144C8, and the design need about 1300 cells. when I try to use LogicLock to constraint my design, I failed. and the following is the error message: ...
Altera_ForumHonored Contributor
Honored Contributortake a look at the architecture:
http://www.altera.com/literature/hb/cyc/cyc_c51002.pdf the Cyclone lab contains 10 LEs. in Chip Planner, you should be able to identify the LABs (vs the M4K, etc), and draw a region containing enough for your design why are you using LogicLock?
