Forum Discussion
Error during VIP simulation verification
Using VCS tool, establish a VIP simulation environment according to the steps in the Avalon-ST Video Verification IP Suite chapter of Appendix A of the VIP User Guide
However, when loading the last file in the list in the simulation, an error was reported. The error information is shown in line 1100 of the log file:
Error-[IPS] Illegal part select
, unknown line number
In following verilog source, cannot take part select of the following
expression:
PACKET_TRANSFER_RSP_WCMD_DONE."./../../dut/ip/dut/dut_alt_vip_cl_vfb_0/alt_vip_packet_transfer_191/sim/synopsys/src_hdl/alt_vip_packet_transfer_write_proc.sv",
25
1 error
CPU time: .085 seconds to compile
Chronologic VCS (TM)
Version N-2017.12-SP2_Full64 -- Tue Dec 10 11:06:00 2019
Copyright (c) 1991-2017 by Synopsys Inc.
ALL RIGHTS RESERVED
2 Replies
- RichardT_altera
Super Contributor
Hi Chris,
The Video and Image Processing IP cores support only ModelSim* simulation software.
Reference: 5.1.1. Specifying IP Core Parameters and Options
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_vip.pdf#page=40
Please use Modeisim for VIP simulation.
Best Regards,
Shyan Yew
- CCheng
New Contributor
Hi Shyan,
Got it.
Thanks for your help!