Honored Contributor
Honored ContributorWell, based on "engineering judgement" and experience... If one combination exists preventing operation even with JTAG, you've hit it... (other might call it "Murphy's law"...)
Nevertheless - if the JTAG chain is valid (as the Device is detected in Programmer window / JTAG chain check completes) there might be something else... Have you checked the power lines are all avaliable (VCCINT, VCCPLL and VCCIO) and stable during and with end of JTAG datatransfer? Perhaps there are some pins connected by the FPGA (as being the default for unused ones) to GND that are low ohmic connected to VCCIO on your board... Otherwise I'm running out of ideas :-/
