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DPate8's avatar
DPate8
Icon for New Contributor rankNew Contributor
7 years ago

Error (10477): VHDL error at add_sub.vhd(57): name "add" must represent signal How to solve this error? Thanks.

LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_signed.all; -- Entity Declaration ENTITY add_sub IS PORT ( A,B : IN STD_LOGIC_VECTOR(3 downto 0); SEL : IN STD_LOGIC; S...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Line add <= s1;

add is variable right, check the assignment to a variable.

must be like add := s1;

Please note that, I have not checked the complete code.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand