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Altera_Forum
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15 years ago

Error 10200

Hi Everyone, When trying to synthesize the following code I get the error: Error (10200): Verilog HDL Conditional Statement error at prog_counter.v(62): cannot match operand(s) in the cond...
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Altera_Forum
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9 years ago

Thank you, I had the same problem. Worked for me too.