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Altera_Forum
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15 years ago

Error 10200

Hi Everyone, When trying to synthesize the following code I get the error: Error (10200): Verilog HDL Conditional Statement error at prog_counter.v(62): cannot match operand(s) in the cond...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Figured it out, it was the fact that the second always block was sensitive to the trigger. I removed it from the event list and just sync the trigger to the clock before it reaches this module.