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Altera_Forum
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11 years ago

error 10170: HDL syntax error in Verilog

Hi, i got some trouble for the code i developed: when i execute this code: if(rst==1'b1) begin 38. cs [0] = 4'b0; 39. cs [1] = 4'b0; 40. cs [2] = 4'b0; 41. cs [3] = 4'b0; 42. cs...
Altera_Forum's avatar
Altera_Forum
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11 years ago

I solved that error! :)

we should declare always(posedge...) instead of always (edge...) in Verilog. :)