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Altera_Forum
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13 years ago

error : cant" resolve multiple constatn driver for...

Hi. I am making digital clock, and I have problem..

When i insert the red letters, errors rise. ( when I remove the red letters, errors is removed.

error : Error (10028): Can't resolve multiple constant drivers for net "hour_2p[x]" at counter_test01.vhd

Error (10028): Can't resolve multiple constant drivers for net "minute_2p[x]" at counter_test01.vhd Error (10028): Can't resolve multiple constant drivers for net "second_2p[x]" at counter_test01.vhd

what does " cant't resolve multiple constant drivers for net ~ " mean?

How can I remove the errors?

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY counter_test01 is

port(

button0 : in std_logic; -- mode_change

button2 : in std_logic; -- time_select_up_key, and select_key

button1 : in std_logic; -- time_select_down_key

sw9 : in std_logic; -- select_key

seven_seg0 : out std_logic_vector (7 downto 0);

seven_seg1 : out std_logic_vector (7 downto 0);

hour_2p : out std_logic_vector(5 downto 0); -- hour

minute_2p : out std_logic_vector(5 downto 0); -- minute

second_2p : out std_logic_vector(5 downto 0); -- second

rst_n : buffer std_logic; --active_low_reset

clk : in std_Logic); --clock_pulse

end counter_test01;

ARCHITECTURE arc of counter_test01 is

signal clock_count : std_logic_vector(3 downto 0);

signal second_pulse : std_logic;

signal minute_pulse: std_logic;

signal second_count : std_Logic_vector(5 downto 0);

signal minute_count : std_logic_vector(5 downto 0);

signal hour_count : std_logic_vector(5 downto 0);

signal button0_sg : std_logic_vector(2 downto 0);

signal button1_sg : std_logic;

signal button2_sg : std_Logic;

constant clock_cnt : integer := 9; -- 10Hz to 1Hz

constant second_cnt : integer := 59;

constant minute_cnt : integer := 59;

constant hour_cnt : integer := 23;

constant zero : integer :=0;

constant six : integer :=6;

begin

process(rst_n,button0,sw9)

begin

if(rst_n ='0') then

button0_sg <= (others =>'0');

button1_sg <= '0';

button2_sg <= '0';

elsif(button0'event and button0 = '1') then

if(button0_sg < six) then

button0_sg <= button0_sg + 1;

end if;

end if;

end process;

process(rst_n,clk)

begin

if(rst_n ='0') then

clock_count <= (others =>'0');

second_pulse <= '0';

elsif(clk'event and clk ='1') then

if clock_count < clock_cnt then

clock_count<= clock_count + 1;

else

clock_count<= (others => '0');

end if;

if clock_count = clock_cnt then

second_pulse <='1';

else

second_pulse <= '0';

end if;

end if;

end process;

process(rst_n,clk)

begin

if(rst_n ='0') then

second_count <= (others => '0');

minute_pulse <= '0';

second_2p <= (others => '0');

elsif(clk'event and clk = '1') then

if (second_pulse = '1') then

if second_count < second_cnt then

second_count <= second_count + 1;

else

second_count <= (others => '0');

end if;

end if;

end if;

end process;

process(rst_n,clk)

begin

if(rst_n ='0') then

minute_count <= (others => '0');

minute_2p <= (others => '0');

elsif(clk'event and clk = '1') then

if (second_count = second_cnt and second_pulse = '1') then

if minute_count < minute_cnt then

minute_count <= minute_count + 1;

else

minute_count <= (others => '0');

end if;

end if;

end if;

end process;

process(rst_n,clk)

begin

if(rst_n ='0') then

hour_count <= (others => '0');

hour_2p <= (others => '0');

elsif(clk'event and clk = '1') then

if (second_pulse = '1' and second_count = second_cnt and minute_count= minute_cnt) then

if hour_count < hour_cnt then

hour_count <= hour_count + 1;

else

hour_count <= (others => '0');

end if;

if hour_count = hour_cnt then

rst_n<= '0';

end if;

end if;

end if;

end process;

-------------------------------------------------------------

------------------------------------------------------------- time 24LIBRARY IEEE;

process(rst_n)

begin

if(button0_sg = "000") then

second_2p <= second_count;

minute_2p <= minute_count;

hour_2p <= hour_count;

end if;

end process;

end arc;

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I can see your hour_2p, minute_2p ... also assigned in reset of previous process. So just remove them from there and reset them in their last process.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    And to complete kaz' answer, "cant't resolve multiple constant drivers for net" means that you are assigning a value to the same signal in different places, either from several processes (which is the case here), from several concurrent statements in the architecture, or a combination of both. While this is valid in VHDL, it isn't synthesizable.