Forum Discussion
Altera_Forum
Honored Contributor
10 years agoHi,
the mentioned device has four pins used for boundary-scan testing/in-system programming (ISP) or as I/O pins, according to the programmed content. If these pins are switched to I/O then the device is accessible via parallel protocol for off-line programming only instead of serial JTAG protocol for ISP. The parallel programming protocol is supported with Altera Programming Unit APU from the manufacturer or the 3rd party programmers such as BPM, Data IO, Elnec or System General. Or the CPLD is broken and further read-out is not possible. These devices have security bit for protection so read-out can lead to incorrect content if programmed with the security bit. Regards, Martin