EPF10k10 configuration time?

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Anyone know the absolute maximum total configuration time for the 10k10? ( POR + EPC1 configuration time). I seem to recall it being somewhere around 320ms but don't know if that includes POR time...

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I had a dig around in some old Altera application notes and found an old one with the numbers you want. This info might be in other documents too, but since the app is no longer on the Altera site, I'll upload it here. I searched for POR and DCLK and found the following (you can read the app for details).

From AN116:

1) p9 EPC devices have a 200ms (max) power on reset.

2) p42 PORSEL delay 2ms or 100ms (depends on your board)

3) p6 EPF10K10 configuration size is 118,000-bits, p32 DCLK maximum 16.7MHz, so about 7ms configuration time.

That's 307ms, so your estimate of 320ms seems reasonable if you're using the longer PORSEL setting.

Cheers,

Dave

That's a mighty long time :-) Thanks (again) Dave!

-Mux

I used Windows 7. I want to make new design on LP-2900 for CPLD-EPF10K10.

I tried on Quartus-II, But CPLD-EPF10K10 is not supported by Quartus-II.

So Please suggest me which software support CPLD-EPF10K10 for Windows 7.

Please reply ASAP.

Download and install Quartus 9.0SP2 Web Edition

ftp://ftp.altera.com/outgoing/release/

I don't know if that version will work under Windows 7, so my recommendation would be to download VirtualBox and install Windows XP, and then install Quartus 9.0SP2 in the virtual machine.

Cheers,

Dave

Runs fine under windows 7...

-Mux

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Runs fine under windows 7...

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Good to know, thanks!

Cheers,

Dave

FWIW, I settled on a TC32M from microchip with a minimum reset time of 500ms. Seems to do the job nicely!

-Mux

Howdy!

Been a loooong time since but I've got another question on the EPC1 (and 2) \INIT_CONF reset. From what I gather the config device will pulls this low to initiate configuration as it's connected to \CONFIG on the FPGA. Now, with \INIT_CONF being open drain, I should be able to connect this to a PMIC reset output, correct? That way, the FPGA gets configured first whereas the pushbutton device on the PMIC would re-initiate the config phase. Nice thing about this is that I can use CONF_DONE to hold my CPU in reset.

Question I have is what happens when I hit reset *during* the configuration phase? Does that mess everything up?

Cheers,

-Mux

Hi Mux,

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what happens when I hit reset *during* the configuration phase? Does that mess everything up?

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It might. I recall using TinyLogic buffers to isolate signals that the data sheet indicate were bidirectional, but I'd have to look in the schematics ... so lets look at the EPF10KE100 boards ...

https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

https://www.ovro.caltech.edu/~dwh/correlator/pdf/digbase_sch_rev_c1.pdf

https://www.ovro.caltech.edu/~dwh/correlator/pdf/correlator_sch_rev_c1.pdf

digbase p32 has the EPC2, INIT_CONF# connects to SC_PS_CONFIG#, which goes to the FPGA on p42. p46 has the reset circuit, with the push button connection.

Read the comments on p32 (top left). If your reset is connected to the INIT_CONF# signal, then yes, you will initiate reconfiguration.

I used a slightly different approach on this board;

https://www.ovro.caltech.edu/~dwh/carma_board/index.html

https://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf

Look at p95 on the schematic. In this design the CONF_DONE signal is used to generate the reset at the end of the configuration. Because CONF_DONE is bidirectional, I added the buffer to isolate the CONF_DONE signal from the push-button reset.

These examples might give you some ideas for your design :)

Cheers,

Dave

As always, Dave delivers! Thanks man!

Mux