Altera_Forum
Honored Contributor
Honored ContributorEPC20, VHDL Divider & PLL Question
hello,
not sure if this is the 'correct' sub-board in which to post these related questions....
i'm a newbie student of fpgas and vhdl. my setup:
2.6 ghz amd-64 with 4 gigs of ram
winxp pro sp3
terasic de1 development board w/cyclone ii, epc20-f484-cn7 fpga
hp8116a 50 mhz function generator
tektronix 2246 four channel oscilloscope
agilent frequency counter
quartus ii, v9.1 sp2, webed !! (thanks...altera)
the function generator output is set for 24 mhz, pulse-width 10% duty, with v[sub]ih = [/sub]+1.5 ~ +1.7 vdc wrt dc return (gnd). the generator is connected via rg-174u coax cable to the ext_clock input (sma) pin_m21 on the terasic de1 dev-board.
goal:
divide a clock signal down using a d flip-flop binary divider chain. 24 mhz / 23bits = 1.41 hz.
configuration:
the output signal is monitored via ledg[7], (de1-pin_y21) which is conncted to the last bit of the d-ff divider chain of the routed synthesized circuit. the divider chain is a 23 bit up incrementing binary counter which is being used to numerically divide-down the 24 mhz clock, in an attempt to generate an appx 1.4 hz signal.
problem:
the wrong signal frequency is being produced with (suspected...hoped for?) proper divide ratio.
perceived results:
applying 24 mhz pulse signal to divide-by binary counter, d-flip-flop divider chain generates proper simulation waveforms as can be seen in the simulation (screen-grab image provided below), but the output signal period is much too long. using 23 bits to divide the clock signal is given mathematically to be correct divide ratio, while, experimentally, it is found that 11 bit divide ratio generates desired result.
method:
24 mhz = 24[sup]+6[/sup]
24[sup]+6 [/sup]/ 23 bits (8,388,608) = ~1.43 hz
unfortunately, i don't see 1.43 hz on blinker_o (q23), instead, i see something on the order of 2 ~3 minutes per cycle when it is expected to be 1.43 hertz.
however, if i change the n_bit generic value from a divide ratio of 23 down to 11 (appx 1/2) i do see, appx 1.43 hz. i am confused, i do not understand what is happening? what am i missing?
and then, another question unrelated to the clock-divider problem, in reading through cyclone ii epc20 data-sheet, i see that there are plls that are available. how are those resources accessed using vhdl, or via any other manner?
below is the vhdl code for the divide_by_counter led "blinker", which is the 'top' level:
-- Dependencies:
-- Quartus II, v9.1, SP2
--
-- Description: Clock divide by N_BITS counter 'blinker'
--
-- Code Rev: rev 0.01 - file created
-- Additional Comments:
--
-- Development Platform: Terasic DE1, EPC20-F484-C7N
--
-- by altera_student, 05-22-2013
--
---------------------------------------------------------------------------
--
-- library declaration
library IEEE;
use IEEE.std_logic_1164.all; -- basic IEEE library
use IEEE.numeric_std.all; -- IEEE library for the unsigned type and
use IEEE.std_logic_unsigned.all; -- to overload the '+' operator
entity blinker is
generic (N_BITS : integer := 23); -- 'divide by' value
port(
clk_i : in std_logic;
blinker_o : out std_logic_vector((N_BITS-1) downto 0)
);
end blinker;
------------------------------------------------------
-- 12,000,000 Hz clock / 22 bit counter (8,388,608) = 1.43 Hz
-- 24,000,000 Hz clock / 23 bit counter (16,777,216) = 1.43 Hz
-- 24,000,000 Hz clock / 11 bit counter (2048) = 11718.75 Hz
architecture behav of blinker is
signal cnt_r : std_logic_vector((N_BITS-1) downto 0);
begin
-- divide clk by n_bits
process(clk_i) is
begin
if rising_edge(clk_i) then -- clock on the hi pulse
cnt_r <= cnt_r + 1; -- increment the bin counter
end if;
end process;
blinker_o <= cnt_r; -- update the outputs, pickoff last bit for output signal
end behav; -- blinkerhere's a screen-shot of quartus sim depicting that the 11 bit version binary counter is producing proper waveforms:
https://www.alteraforum.com/forum/attachment.php?attachmentid=7284
so the question is, why isn't the circuit producing the correct output frequency? whats going on? with 24 mhz input, an 11 bit counter should produce 11,718.75 hz, not 1.41 hz?
any suggestions will be appreciated (aside from jumping into a lake), <g>
thanks in advance,
altera_student
