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Altera_Forum
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12 years ago

EPC20, VHDL Divider & PLL Question

hello, not sure if this is the 'correct' sub-board in which to post these related questions.... i'm a newbie student of fpgas and vhdl. my setup: 2.6 ghz amd-64 with 4 gigs of ram ...
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Altera_Forum
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12 years ago

There is nothing that strikes me as bad here, except that you are using both numeric_std.all and std_logic_unsigned.all at the same time, which is usually a bad idea and confuses the synthesizer. I would suggest to only use numeric_std.all and declare your cnt_r signal as an unsigned instead of std_logic_vector. If you want to keep blinker_o a std_logic_vector, you can cast it with this line outside of the process:

    blinker_o <= std_logic_vector(cnt_r);  -- update the outputs, pickoff last bit for output signal
Are you sure the FPGA is picking the clock correctly? You could compile a simple design that would recopy the clk_i signal to an outside pin and check with an oscilloscope that it is indeed 24MHz.