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Altera_Forum
Honored Contributor
Honored ContributorEPC20, VHDL Divider & PLL Question
hello, not sure if this is the 'correct' sub-board in which to post these related questions.... i'm a newbie student of fpgas and vhdl. my setup: 2.6 ghz amd-64 with 4 gigs of ram ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The function generator output is set for 24 MHz, pulse-width 10% duty --- Quote End --- You have a pulse that is at '1' state for 4.17ns. It may violate timing constraints. Clock signal should be 50% duty cycle, I think.
