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You may have this low impedance value between BGA balls before powering up the device. It's quite normal for a un-powered up FPGA, so we do not measure that.
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It seems to me, that the Altera support person isn't familiar with Cyclone III technical data, particularly the hot-socketing specification. Low impedance can be possibly expected for supply pins, but not for I/O. The specification doesn't tell an input resistance, but guarantees |Iopin| < 300 uA for the unpowered FPGA and during power-up. Reading the specification strictly, the measurement current shouldn't be too small when checking for circuit shorts with an in-circuit tester.
Solder shorts and ESD induced damage are a possible explanation, generally. After you sorted out the former, EOS should be considered. I can't determine the likelihood for the specific process, you have to check it thoroughly. In my opinion, massive ESD issues in the process can be explained only by either complete ignorance to handling rules or badly designed process equipment.
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