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Very strange. You should contact Altera.
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I did contact Altera - the first thing I did when I was seeing the fault moving with the FPGA's. This issue is very urgent for us, as it is holding up one of our lines-
This is the ramblings I got back from Altera.
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Hi Steve
Apologize for the delay in response as the SR was floating over and only routed to me today.
The lead-free device reflow temperature is in the 245°C to 260°C range, depending on the package size (Table 2 on page 5). From the temperature profile provided, it seem customer using lower temperature, 230°C-240°C. I recommend they check their reflow profile against our recommendations and also the handling procedure of the devices before manufacture, this includes storage and baking before reflow. Please refer to AN353 for the recommended lead free device reflow profile.
You may have this low impedance value between BGA balls before powering up the device. It's quite normal for a un-powered up FPGA, so we do not measure that. You may have this low impedance value between BGA balls before powering up the device. It's quite normal for a un-powered up FPGA, so we do not measure that. If you measure on the powered up board, and find that the IO pins is almost short to ground, it may have several possibility to have caused this:
First is the short circuit in the board trace, and second would be the EOS (electrical over stress) issue. This may be caused during reflow or just by someone touching the device or board without discharging themselves first. If the IO pin is by any chance supplied with the voltage or current larger then the absolute maximum rating mentioned in the handbook, it will cause permanent electrical damage to the IO buffer.
In order to avoid electrical damage, the device should always be handled in a static-free environment and all the input signals should remain within specified limits, as recommended in the Altera Data Book, at all times.
Thank you for contacting Altera mySupport.
Regards
Ai Phing
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