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Altera_Forum
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10 years ago

EP2S60F1020 device testing

Hello

I am doing functional testing of EP2S60F1020 using JTAGAfter doing power up pins are getting auto assign as per program.

BSDL file downloaded from net is not working.

Please help.

Best Regards

Nikhil

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Depending on the configuration scheme chosen, the FPGA will always try to configure at power up. If there's a valid configuration image then it will always boot and assign the pins 'as per program'. I assume that's what you refer to.

    However, you should always be able to take control of the FPGA, via JTAG. Occasionally BSDL files have faults in them. However, with a mature series, like Stratix II, this shouldn't be the case.

    Download the BSDL file again. Make sure you take it from the "stratix ii bsdl files (https://www.altera.com/support/support-resources/download/board-layout-test/bsdl/stratix2.html)" page.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Dear Alex

    I am facing problem in VIT test at the node of two FPGA node are interconnected.

    Best regards

    Nikhil
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Dear sir

    I am doing a functional testing of PCB.

    Which having two BGA and both having JTAG access.

    Generally in other boundary scan device I am able to use I/O as a vertual external. It get configure as a input or output as per my programming through JTAG .

    But in this device it is getting predefine as per the program store in it.

    In vit (vertual interconnection test) track between two BGA are check for that both device pin should work like bidirectional but it is getting predefine either as a input or output as per designer programming.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Which specific package are you using and which pins are causing the problem? There are certain pins whose function you will not be able to change via JTAG.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Dear Sir

    I am using BGA package, and i do agree with you that family pin will not change via jtag.

    Anyway

    Today i erase the program of FPGA after that it is working fine. My problem is almost solved.

    But Still i wants to know the technical reason behind it if any.

    Thanks for support.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I'm glad you're getting somewhere. I can't comment on the 'technical reason why' without knowing the specific issue, the specific pins and which BGA package you're using. If you need further help post those details here.

    Cheers,

    Alex