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Altera_Forum
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10 years ago

EP2S60F1020 device testing

Hello I am doing functional testing of EP2S60F1020 using JTAGAfter doing power up pins are getting auto assign as per program. BSDL file downloaded from net is not working. Please help. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Dear sir

I am doing a functional testing of PCB.

Which having two BGA and both having JTAG access.

Generally in other boundary scan device I am able to use I/O as a vertual external. It get configure as a input or output as per my programming through JTAG .

But in this device it is getting predefine as per the program store in it.

In vit (vertual interconnection test) track between two BGA are check for that both device pin should work like bidirectional but it is getting predefine either as a input or output as per designer programming.