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krbreton's avatar
krbreton
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6 years ago

EP1K50 Pin Assignment Issues

We are working with an older Altera EP1K50TC144-1 part. We are using Quartus 9.2 to create programs using Altera HDL (This is a legacy design that we needed to make some small updates to). The FPGA...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
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6 years ago

Hi Kyle,

Thanks for the question, to answer the above question I would like to set the expectation as I do not have the internal document to verify.

But in Generic Quartus environment the pin will assigned to tri state. . The above voltage as per me may be coming from another devices from the board.

krbreton's avatar
krbreton
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6 years ago

We have lifted Pin33 from the board to verify that the voltage is not coming from the board - it is definitely coming from the FPGA itself.

If there are other pins we need to lift to verify, please let me know what they are - this failure is a high priority for us, and we cannot explain this behavior.

-Kyle