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I cann't assemble any until now.The connetcion was there when seen in RTL ,but lost in techology map viewer. This maybe mean that it is not because the connection that I neglect,but the fitter or synthesis's judgement for that model output of that input pin always stuck at GND ,known from warning,so they just omit their input pin's connection. Anyone here have better ideas?
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Hi ,
define your component as design partition. This will preserve the IF of the component.
If the root cause of the problem is in the block driving the component, you should see which signal(s) are tied to VCC or ground .
Kind regards
GPK
Honored Contributor
