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noujaz's avatar
noujaz
Icon for New Contributor rankNew Contributor
4 years ago

Enabling series termination on 1.0V and 3.3V IOs in MAX10 FPGA

Hi All, Can I enable series termination on 1.0V IOs of MAX10 FPGA. "MAX 10 General Purpose I/O User Guide" does not mention series termination options for 1.0V and 3.3V IOs. Also when I tried addi...
ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
4 years ago

In the MAX10 GPIO User Guide, per Table 13. Selectable I/O Standards for RS OCT indicates that On Chip Termination (OCT) is only available for 1.2V thru 3.0V LVCMOS, 1.8V thru 3.0V LVTTL, as well as SSTL and HSTL outputs. Not possible for 1.0V or 3.3V LVCMOS. So you are trying to select an option that is not possible, and Quartus is letting you know that.

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hello,

    Yes, the designer need to refer to our documents for FPGA limitations. I will close this case in 3 days if there is no further question from you.

    Thank you.

  • noujaz's avatar
    noujaz
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi,

    Thanks for your input. I have one more question here. What will happen if I declare the IO pins in a bank as 1.2V in the Quartus Pin Planner and connect 1.0V to FPGA VCCIO pins on the board? I will make sure the source and destination IOs are working on 1.0V voltage so that the pins will not get damaged. If this is possible I can enable series termination inside FPGA on the lines I need.

    Thanks,

    Noujaz