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AGofs's avatar
AGofs
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Emulated LVDS outputs and Quartus pin planner

At "CycloneV device handbook" wrote: "Emulated LVDS, RSDS and mini-LVDS output buffers use two single-ended output buffers with an external single-resistor or three-resistor network, and can be tri-...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

i am sorry for late response ,Actually caught into other stuff and didn't pay attention my open issues.I think you can do simulation after the buffer level (ie Single ended) and when you use in quartus XX_n pin automatically assigned by quartus if the IO std selected correctly.

Is that make sense ?

Thank you ,

Regards,

Sree