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Altera_Forum's avatar
Altera_Forum
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8 years ago

EMIF oct_rzqin compile error!

Hi,

I have generated a Qsys design of NIOS + EMIF(DDR4), when running synthesis in Quartus Prim Pro v17.0, it reports error:

Error(17044): Illegal connection on I/O input buffer primitive i_nios|nios_emif_0|nios_emif_0|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.ibuf. Source I/O pin i_nios|nios_emif_0|nios_emif_0|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf drives out to destinations other than the specified I/O input buffer primitive.

Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.

I'm sure the EMIF pin oct_rzqin is connected to top level input, not driving anything else in my RTL.

Thanks.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Since you are using Pro, you might want to try BluePrint to create a legal placement for the EMIF.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi,

    the error is reported during "Analysis & Synthesis", Blueprint cannot open without completion of "Analysis and Synthesis".

    the error is within EMIF IP, please suggest how to solve the problem.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    if you are probing that signal with sigtap , it may cause you a problem

    so delete it from sigtap
  • gsaman's avatar
    gsaman
    Icon for New Contributor rankNew Contributor
    6 years ago

    The error is saying that your IO pad is sourcing to multiple destinations. Your IO Buffer and some other input. This connection to multiple destinations is illegal for IO Buffers. Most probably you have signal tap connected.