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Altera_Forum
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8 years ago

EMIF oct_rzqin compile error!

Hi, I have generated a Qsys design of NIOS + EMIF(DDR4), when running synthesis in Quartus Prim Pro v17.0, it reports error: Error(17044): Illegal connection on I/O input buffer primitive ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

the error is reported during "Analysis & Synthesis", Blueprint cannot open without completion of "Analysis and Synthesis".

the error is within EMIF IP, please suggest how to solve the problem.

Thanks.