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VenkateshK's avatar
VenkateshK
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

EMIF DDR4 STRATIX 10 ,QUARTUS PRIME PRO 20.1

Hi, I have Generated example design for emif stratix 10 and simulation scripts too. While simulating in the modelsim ,every signal has default values only. even calib_success&fail both were low only...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Venkatesh,


I think the time for finishing calibration should be around 30 minutes or more but it's depends on the device that has been used.


Is there any transaction in the log?


I think you need to let the design run -all and finishes the simulation.

It's will give you the result at the end.


Regards,

Adzim


VenkateshK's avatar
VenkateshK
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

YES sir, I did run -all only ,its been more than 2 hours ,still calib_success is low only!

I have been using Stratix 10 EMIF.

in log:

initializing RAM with calibration code ... ed_sim.emif_s10_0.emif_s10_0.arch.arch_inst.io_ssm_inst.io_ssm.inst.<protected> @ 2750 ps

after this empty.

what could be the issue?

Sir,do you have any code for custom data write and read instead of traffic generator?

  • VenkateshK's avatar
    VenkateshK
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    one more thing sir,

    at the end of compilation ,getting critical warning "DDR4 Timing Requirements not met".

    In SDC file, I have created clocks for pll_clk and user_clk!

    Is problem is related to timing issues?