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Altera_Forum
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12 years ago

Embed sdc constraint in vhdl design file - help needed

Hi everyone! I'm trying to set a sdc constraint into one of my vhdl design files. I want to constrain a muliticycle path inside that entity and I want it to go with the design file to reuse it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Many thanks for the fast reply!

Yes, from the sdc file it is working.

I reviewed the Quartus processing output and found the section where it says "Evaluating HDL-embedded SDC commands". There are a number of commands listed but all of them are from altera megafunctions and none of them is related to my design file. My command from the design file is just not listed. It seems as if it is not processed.