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Altera_Forum
Honored Contributor
Honored ContributorEmbed sdc constraint in vhdl design file - help needed
Hi everyone! I'm trying to set a sdc constraint into one of my vhdl design files. I want to constrain a muliticycle path inside that entity and I want it to go with the design file to reuse it ...
Altera_ForumHonored Contributor
Honored ContributorDoes it work from the separate SDC file or inputting it directly into timequest? I ask this because it may not be a problem with the attribute etc - but maybe the synthesisor removed the registers or the heirarchy isnt the same name and timequest cannot find the start/endpoint.
Are there any warnings in timequest about not finding any nets?
