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Honored Contributor
Honored ContributorEfficient Verilog coding style
When I changed from using MegaFunctions to Verilog and used wires for the combinatorial logic there was higher speed and less resources(I think). Specifically it was for an ALU, so it seems the ALUT function was more efficient. Are there any guidelines for efficiency of implementation? This is for StratixIII which has a new LUT design.
Continuous assignment for each alu function and a case selected the wire for output. Thankyou11 Replies
Altera_ForumHi SimKnutt
Since you used wires and comb logic may be you have opted unknowingly for asynchronous design. That is much faster but hard to master against hazards and logic delays. If there are no registers there would be no violations of reg timing and no limit for fmax from reg point of view
