Efficient Verilog coding style

There are certainly plenty of coding style's effect on efficiency , though not per device type.

The LUT implements comb logic functions but the rtl methodology recommends using clocked register afterwards and that is why the fpga architecture is based on units of LUT followed by a register. Too long comb paths could violate timing.

There are no strict rules that every LUT/reg pair should be used as such but you may skip some regs or use borrow extra regs.

At the end your design is supposed to transfer logic decisions such that a reg level hands it to next logic and reg level.

This approach helps achieve timing as well. Every launch register is utilised (with delays) to meet timing of latch reg.

If you don't use registers then you need to apply your own asynch techniques (I don't anything about it).

Presence of clock or pll is part of the story. So does presence of object reg but what matters is how many regs are clocked on the clock edge as the sampling point.