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Altera_Forum
Honored Contributor
Honored ContributorEfficient Verilog coding style
When I changed from using MegaFunctions to Verilog and used wires for the combinatorial logic there was higher speed and less resources(I think). Specifically it was for an ALU, so it seems the ALUT...
Altera_ForumHonored Contributor
Honored ContributorIt would be helpful if you would focus on the question "Are there coding style guidelines to get the most efficient use of Stratix III ALUTS". The alu is combinatorial logic and that means the signal flow is not clocked. just as in any design. NOTHING NEW OR DIFFERENT OR ASYNCHRONOUS. As best that I can tell, combining the mux and data flow functions resulted in fewer ALUTS. By the way, the PLL in the design may give you a clue that there is clocking.
