Efficient Verilog coding style

I am afraid I will come back to my same first conclusion. If you look at the number of registers used in your project then you will find it is only one single rgister.

Your design is therefore not RTL based and will fail functional simulation unless you know how to design asynchronously whci is so far not standardised.

By the way, a company called Achronix (I believe) were talking about their new fpgas based on asynchronous design (no clock) and hence very very fast yet the design methodlogy would use conventional RTL to keep it easy. Their tool would convert the user RTL to their asynch architecture. However, that was 4 years ago and I until now I don't hear of their product coming to the market. May it was a failed venture