Eagle ulp script to generate FPGA schematic connection directly from qsf?

Hi,

I use cadsoft eagle to create schematics and pcb.

I use the "make-symbol-device-package-bsdl.ulp" script to create FPGA library.

But then I have to connect manually each fpga pin to a wire, label it...

I am designing a board with a F40 FPGA and I don't want to do that. It takes to munch time and errors are very hard to find. Moreover any quartus pinout modification is a nightmare :-/

So I am looking for a script to:

1) verify that the FPGA is present on the selected schematic sheet

2) parse qsf file

3) create wires connected to corresponding fpga pins and correctly labelled

example:

- select a schematic sheet with a fpga

- run script (with qsf and fpga part name as input)

set_location_assignment PIN_R19 -to epcs_clk => a wire named "epcs_clk" is created, labeled and connected to fpga pin R19

Is it possible to write an ulp script able to do that ?

Thanks in advance for advice.