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ADhar4's avatar
ADhar4
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4 years ago

Each power on communication data corruption

Hi, We made a custom design using cyclone 5 FPGA device. This board has Ethernet, SFP, RS422 communications & discrete signal as input & output ports. The functionality is Board will recei...
Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

I am Farabi supporting this case. May I request further information like any screen shot of waveform of SFP or indication that showing intermittent transmission failures. We can start our debug form that point.

,

information that might help us to debug:

1. what speed you run for RS422 (max 10Mbps)

2. how long is your RS422 cable?

3. If you use short cable (less than 10m) is the intermittent failure still persist?

regards,
Farabi

  • ADhar4's avatar
    ADhar4
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi Farabi,

    Thanks for your response. Please find attached screenshot of output data packet details.

    1. what speed you run for RS422 (max 10Mbps) - Max baud rate : 38400

    2. how long is your RS422 cable? - Less than 2m cable

    3. If you use short cable (less than 10m) is the intermittent failure still persist? - Yes

    For better understanding explaining details again, have a design with Cyclone v transceiver native phy IP. Logic receive UART data and framing it with header, tailor and sending it to IP.IP send it serially to SFP fibre cable which is loopbacked to the same board and data from the fibre is getting deframed and send it to UART again. I programmed FPGA using memory(JIC file, SOF is converted to JIC for memory configuration).I loaded my code into flash it was working fine .If i power off my board, the output is null with the same working code. But it's happening occasionally on the power sequence. Any help on this!!!!

    • Farabi's avatar
      Farabi
      Icon for Regular Contributor rankRegular Contributor
      4 years ago

      Hi,

      Is it possible to loop back the SFP internally? I mean the data does not going through loopback cable, instead, the output of SFP connected to input of the SFP module internally. This is to filter out PHY and cable issue, and focus to the internal data processing issue.

      regards,
      Farabi

      • Farabi's avatar
        Farabi
        Icon for Regular Contributor rankRegular Contributor
        4 years ago

        Hi,

        We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

        regards,
        Farabi