Dynamic Reconfiguration: reconfig_clk pin

Hello, I'm using the Cyclone IV's ALTGX_RECONFIG megafunction. I would like to know if there are any constraints on the clock that drives the reconfig_clk port? Does this clock need to be a differential clock to the FPGA?

Currently I am using a single-ended clock and have connected it to CLKIO5/DIFFCLK_6P pin on the FPGA (EP4CGX150DF31). I'm not sure if it would be better to connect the clock on one of the REFCLK[0..2] pins.

Thanks,

joe