Dual Port Ram problems : Synthesizes error with one or two clock signals

Hello,

I was running in a problem and can't find a way out . Although there are already a lot of posts concerning problems with dual port rams, I couldn't found a solution. I am using a DE1 board, based on the CyclonII EB2C20F484C7, using Quartus 9.1, SP2. My goal is a dual clocked true dual port ram to be able to read/write on both ports. I was trying the ALTERA altsynram and altpram megafunction with the frustrating result: Selected device has 52 RAM location(s) of type M4K. However, the current design needs more than 52 to successfully fit. I still can't understand this, because I striped down my design to: 6200 16 Bit words which results in a usage of 25 x M4K blocks from 52 available M4K blocks.

Anyway, I decided to write my own dual port ram code in verilog (See my posted code) . First time, it was looking good: I was able to write to port A and read from port A and I was also able to read the written data from port B ..... BUT--- I was not able to write data to port B. With reference to to the post from ammar ( September 23rd, 2010), I was in th opinion that my problem is related to the usage of 2 clocks. I did write a clock-domain- mux ( code also posted ) to bring my dual port ram design up and running with one clock source . ..... BUT--- the same problem. synthesizes error

I do not know how to proceed now any more and every help is very welcome.

Datails concerning my project can be obtained from my homepage.

My questions:

A) Is my verilog code wrong ?

B) Is the CyclonII EB2C20F484C7 to small or did I use the wrong libraries ?

May be you also have other ideas , how I can solve the problem differently

Many thanks in advance,

Reinhard