Dual-Clock FIFO with clear in Cyclone III

If you have several idle clocks, it technically doesn't matter, but synchronizing the aclr to wrclk is good to have on. That protects the FIFO in case your wren is high out of reset. The reason the read side doesn't get a synchronized version is that it's not necessary. The protection circuitry prevents any reads from occurring since the FIFO is empty out of power-up, so even if rden were high, it is essentially ignored. (And if you disable protection circuitry and do a read out of power-up, well, good luck...)

There are two things I would recommend:

a) Cut timing between the two asynchronous clock domains, if possible. I assume you're using this dual-clock FIFO because there is no relationship between them.

b) If you still have recovery timing violations(like the reset is synchronized in your logic to the read domain, and then directly feeds registers in the FIFO on the read domain, step a) wouldn't cut these paths), feel free to add a false path from your reset control into the DCFIFO:

set_false_path -from [get_keepers your_reset_name] -to [get_keepers *dcfifo*]

(naturally, the names could be cleared up)