DSP Pipelining

Hey guys,

I've been posting on here for a while now, asking questions related to the NLMS senior project I've been working on.

I now have the system working, and have a fully functional RTL simulation. However, when I performed a gate level simulation on the system, I recieved hold errors.

I showed the professor the Verilog, and he said the problem was that we were letting our state machine directly start calculations async. In other words, the posedge of control signals from the state machine activated always loops that began the coefficient update calculations. Such async behavior seems to cause timing issues and glitches.

Instead, he recommended that we peform the calculation operations on the clock edges, and then use if statements to check if the calculations were ready or not.

Upon implementing these changes and making everything change upon the clock edge, we lowered the Fmax down to 10MHz.

We discovered that the calculations were taking too long, so we pipelined them. Now Fmax is up to 60Mhz.

However, we now have 10 clock delays to perform one calculation. The old state machine used to calculate a coefficient, perform a FIR MAC with that calculation, and repeat L times, where L was the tap length of the FIR filter.

Now, there are 10 delays that have to be incorporated into the state machine. It already took 6 cycles just to perform one FIR MAC. Now, with 10 extra cycles, you get 16 cycles to perform one FIR MAC. If you multiply that by the sampling rate , which is 16kHz(Audio), and the number of taps, which is 1024, you get 262 MHz for a required filter clock frequency.

But Fmax is only 60Mhz, even with pipelining!

Any suggestions what to do?