DSP Dev Kit Ethernet & SRAM issue

If your open source SoC does not support the idea of a Tri-state interface, they you're going to have to write some logic to arbitrate access to the bus. For instance, you could simply use the read, write, and chipselect signals to gate control of the bus. If there is the possibility that two components will try to access the bus at the same time then you'll have to write some fancier arbitration logic (like controlling the wait or ready signal to the components).