Honored ContributorHi:
I have drawn a new FPGA board,when I download program in the quartus,it display that I have download the program successfully,but it seems the program doesn't run in FPGA,could anyone tell me why? Thank you!
Honored ContributorWell, you didn't specify some details about your fpga board. How do you download your program, bye JTAG connector or active serial ?
Honored ContributorI download my program with quartus programmer(jtag mode),and the message console displayed success,but the program didn't run at all.
Honored ContributorHow do you know it isn't running?
Regards, ThiagoHonored ContributorIs you software in on-chip memory? In that case did you use the correct HEX file during the Quartus compilation?
Is it in external RAM? In that case did you use the nios2-download software or the IDE to download it? What exception and reset vectors addresses did you set up?Honored ContributorI didn't use a cpu,I just use verilog code,as follows
module CommTest(clk,point,rst,sdram); input clk; input rst; output [3:0]point; output sdram; wire [3:0] point; SDRAM_PLL PLL0(.inclk0(clk),.c0(sdram)); assign point = 4'b1010; endmodule I use JTAG to download,it displayed successfully downloaded,but when I detect the signal of the corresponding pin,all four pins are high.Honored ContributorDid you check the CONFIG_DONE signal from the FPGA?
Is the "point" port assigned to the correct pins? Do you have any warning when you compile the design?Honored ContributorI'm not sure why you need the SDRAM_PLL part in there to debug. Get rid of it and just stick to your "point" wire. Make it as simple as possible. Check that you connected your signal names to pin names (in pin settings) otherwise Quartus will randomly place them wherever it pleases.
