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Altera_Forum
Honored Contributor
16 years agoI didn't use a cpu,I just use verilog code,as follows
module CommTest(clk,point,rst,sdram); input clk; input rst; output [3:0]point; output sdram; wire [3:0] point; SDRAM_PLL PLL0(.inclk0(clk),.c0(sdram)); assign point = 4'b1010; endmodule I use JTAG to download,it displayed successfully downloaded,but when I detect the signal of the corresponding pin,all four pins are high.