Download speed

Hi,

how is the problem related to JTAG speed? Which configuration scheme is implemented for your FPGA?

I'm pretty sure 24MHz is the fastest JTAG can go on the USB Blaster. You can certainly lower the speed if you are having issues.

Dear,

Would u like to help us with the issue as below?

The FPGA which we used is communicated with the MCU, and our previous code has been working fine for a long time. Recently, we added some new modules for the FPGA, and we met an issue, when the MCU reads the FPGA by local bus, some modules are ok, but some did not respond(and some of these modules are not new ). - And we added a 2s delay in the MCU, and read the FPGA again, all the modules are ok. So we suspect that the code has been bigger and the loading time has been longer, and the issue was occurred when the MCU to read it but it loading was not completed. So we originally planned to increase the loading speed.

Is there a situation where some modules are ready and others are not when FPGA loading is not completed? If so, how can we avoid this situation? How we to check the loading status is ok before we operate it? Could we read the config_done signal? Thanks.

Hi,

The issue is not related to JTAG speed. It depends on the FPGA configuration scheme. You should only access the FPGA after nSTATUS and CONF_DONE are asserted, which indicate the device has finished loading and is ready. May I know which configuration scheme you are using (AS, PS, FPP, etc.)?

Regards,

Fakhrul

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