Forum Discussion
FakhrulA_altera
Regular Contributor
3 months agoHi,
The issue is not related to JTAG speed. It depends on the FPGA configuration scheme. You should only access the FPGA after nSTATUS and CONF_DONE are asserted, which indicate the device has finished loading and is ready. May I know which configuration scheme you are using (AS, PS, FPP, etc.)?
Regards,
Fakhrul