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Altera_Forum's avatar
Altera_Forum
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14 years ago

dont care in VHDL problem

Hi Folks,

I am afraid I am asking for some advice again. I am trying to write VHDL code for a 8-3 highest bit priority encoder. I thought it would simply be a code which includes the ‘X’ don’t care value placed in the case statements. However the compiler states that it will be ignored. I suppose I could get round it by writing some if statement which cover all values of X for each input, however this will be long. I don’t mind doing its just if there is an easier method I would rather do it that way.

I have attached the code for a normal 8-3 encoder. Thanks in advance.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY encoder IS

PORT ( CE : IN STD_LOGIC; --Chip Enable

Data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

Data_out: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) );

END encoder;

ARCHITECTURE Encoderbehav OF encoder IS

BEGIN

PROCESS(CE,Data_in)

BEGIN

IF ( CE = '1') THEN

Data_out <= "ZZZ";

ELSE

CASE Data_in IS

WHEN "00000001" => Data_out <= "000";

WHEN "00000010" => Data_out <= "001"; -- 0000001X

WHEN "00000100" => Data_out <= "010";

WHEN "00001000" => Data_out <= "011";

WHEN "00010000" => Data_out <= "100";

WHEN "00100000" => Data_out <= "101";

WHEN "01000000" => Data_out <= "110";

WHEN "10000000" => Data_out <= "111";

WHEN OTHERS => Data_out <= "ZZZ";

END CASE;

END IF;

END PROCESS;

END Encoderbehav;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Remember, that 'X' in VHDL is not "Dont care", it is "Unknown". '-' is "dont care".

    Also, the VHDL rules state that when you compare an array, it looks for that exact string, so

    "----1111" is not equal to "11111111"

    So, for VHDL 1993, there is a std_match function, that allows you to treat "dont cares" as actual dont cares, and allow a real priority encoder. With your current code, if DATA_in is "10000001", the output will be "ZZZ".

    to use std_match, you need to write: 

    
if    std_match("-------1", data_in) then data_out <= "000";
elsif std_match("------10", data_in) then data_out <= "001";
elsif std_match("-----100", data_in) then data_out <= "010";
  
--etc
end if;
    That is all well and good, but VHDL 2008 provides what it calls a matching case, statement, that does exactly what you want, and is supported by the newer versions of Quartus: 

    
case? "data_in" is
  when "-------1" => data_out <= "000";
  when "------10" => data_out <= "001";
--etc
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for mentioning the VHDL don't care syntax and std_match() function.

    In the present case, a simple behavioral description of the priority encoder, scanning the bits in an iteration scheme, seems to be the most conveniant way. If performance is an objective, you should refer to the discussion of priority encoders in the advanced synthesis cookbook.